Silicon Substitution

The story of semiconductor scarcity has been told as a story about lithography. For AI accelerators, it is mostly a story about what happens after the wafer is finished.

An AI accelerator is not a single die. It is a logic die, or several, integrated on a silicon interposer with a set of high-bandwidth memory stacks, mounted on an organic substrate, and packaged. Each of those steps has its own capacity, its own suppliers and its own lead time. The industry's public conversation has focused almost entirely on the first step and almost not at all on the rest.

Tracing the bill of materials

We reconstructed the manufacturing path for accelerator-class parts from equipment orders, substrate trade flows, memory supplier disclosures and published process descriptions. The reconstruction identifies six stages where output can be rate-limited, and estimates capacity and utilisation at each.

The result is unambiguous in one respect: at no point since the third quarter of 2023 has leading-edge wafer capacity been the tightest stage. Packaging assembly has been at or near capacity throughout, and memory qualification has been rate-limiting for specific parts at specific customers repeatedly.

Why packaging is slow to add

Adding packaging capacity is not primarily a matter of buying tools, though tools are part of it. It requires clean-room space qualified to the relevant standard, a trained workforce with process-specific experience, and — critically — a yield learning curve that must be climbed on the specific part being produced. New packaging lines do not begin at mature yield. The ramp is measured in quarters.

The qualification problem

High-bandwidth memory qualification deserves separate treatment because it is the one stage in this chain where capital cannot buy speed. A memory stack must be qualified against a specific controller, on a specific package, under the customer's reliability standard. The process involves accelerated stress testing that takes the time it takes.

This creates a scheduling dependency that ripples through the whole chain. A new accelerator generation cannot ship until its memory is qualified, and qualification cannot begin until sufficiently mature silicon exists. The consequence is that memory qualification, more than any other factor, sets the floor on generational cadence.

Concentration

On every concentration measure we computed — supplier count, geographic distribution of capacity, share held by the largest provider — advanced packaging is more concentrated than leading-edge logic. This is not widely appreciated. The risk profile that follows from it is correspondingly under-analysed.

We do not draw policy conclusions from this. We note only that supply chain resilience analysis that models leading-edge fabrication as the single point of failure is modelling the wrong stage, and that the mitigations appropriate to a packaging constraint differ substantially from those appropriate to a lithography constraint.